(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a capacitor for mixed-mode applications that has low gate resistance.
(2) Description of the Prior Art
The manufacturing of semiconductor devices applies a number of different but interacting disciplines that collectively create high performance semiconductor devices. The majority of these semiconductor devices have as function the processing of digital information which is characterized by zero and one conditions, typically created by on-off conditions of switching transistors. In addition, hybrid functions can be provided that address not only the processing of digital signals but also address the processing of analog signals, either as a function that is provided by one analog semiconductor device or in collaboration with digital devices. Device performance improvements have been sought and established by continuously decreasing device dimensions thereby concurrently increasing device packaging density. This poses problems for a number of the typical analog components such as capacitors and inductors that have physical dimensions that do not lend themselves to ready integration into a highly miniaturized, sub-micron device environment.
The mixing of functions and processing capabilities results in a mixing of components that coexist within one semiconductor device. It is therefore not uncommon to see resistors and capacitors that form part of a semiconductor device which does not negate the fact that the vast majority of device components is made up of transistors, gate electrodes and a variety of switching components that address logic processing functions. Capacitors can for instance form a basic component of analog circuits that are used for analog applications such as switched capacitor filters. Capacitors are also widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor. Mixed mode applications as part of logic processing is expected to find increased application with an emphasis on high frequency applications. Continued reduction in device dimensions has further placed greater emphasis on using copper as an interconnect material, the limitation that this approach experiences however is that the technology of creating capacitive components in a copper interconnect environment is as yet in its infancy, especially where this interconnect environment makes use of the copper damascene process. One process has recently been explored that uses TaN as the material of choice for the creation of the capacitor, this approach however includes the application of an oxide etch stop on the applied TaN material resulting in problems of planarization and etching control and accuracy.
The DRAM technology is widely used for data storage where one transistor and one capacitor form one DRAM cell. For the capacitor a stacked capacitor is frequently used since this structure has good data storage performance characteristics combined with low surface space requirements. To fabricate a DRAM device, a modified CMOS process is typically used. One other application in which the CMOS structure has been successfully applied is in the creation of image sensors.
With the conventional damascene process, a metal via plug is first formed in a surface, typically the surface of a semi-conductor substrate. A layer of dielectric (for instance SiO.sub.2) is deposited over the surface (using for instance PECVD technology); trenches (for metal lines) are formed in the dielectric (using for instance RIE technology). Metal is deposited to fill the trenches; the excess metal on the surface is removed. A planar structure of interconnect lines with metal inlays in the (intralevel) dielectric is achieved in this manner.
An extension of the damascene process is the dual damascene process whereby an insulating or dielectric material, such as silicon oxide, is patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings are also formed. One of the dual damascene approaches uses a dielectric layer that is formed by three consecutive depositions whereby the central layer functions as an etch stop layer. This etch stop layer can be SiN, the top and bottom layer of this three layer configuration can be SiO.sub.2. This triple layer dielectric allows first forming the vias by resist patterning the vias and etching through the three layers of dielectric. The conductive pattern can then be formed in the top layer of dielectric whereby the central layer of SiN forms the stop layer for the etch of the conducting pattern. Another approach, still using the three-layer dielectric formed on the substrate surface, is to first form the pattern for the conducting lines in the top layer of the dielectric whereby the SiN layer again serves as etch stop. The vias can then be formed by aligning the via pattern with the pattern of the conducting lines and patterning and etching the vias through the etch stop layer of SiN and the first layer of dielectric. Yet another approach is to deposit the three layer dielectric in two steps, first depositing the first layer of SiO.sub.2 and the etch stop layer of SiN. At this point the via pattern can be exposed and etched. The top layer of SiO.sub.2 dielectric is then deposited; the conducting lines are now patterned and etched. The SiN layer will stop the etching except where the via openings have already been etched.
Low resistivity metals such as aluminum and copper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. Typical examples of fine line interconnect metals include Al.sub.x Cu.sub.y, ternary alloys and other similar low resistivity metal-based alloys. Emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacturing has led to reliability problems including inadequate isolation, electromigration, and planarization. Damascene processes using metal fill vias and lines followed by chemical mechanical polishing (CMP) with various Al, Cu and Cu-based alloys are a key element of future wiring technologies for very large-scale system integration (VLSI). A key problem is filling high aspect ratio vias and lines without voids or seams, and creating homogeneous structures.
As already stated, copper is at this time explored as an alternate metal to be used as an interconnect metal. Copper has so far not found wide application as an interconnect metal, this despite its relatively low cost, low resistivity, which electromigration resistance and stress voiding resistance. Copper also suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is frequently use as a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a which dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and the substrate. A typical barrier layer is deposited using rf. sputtering of titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN. The barrier layer can also be used to improve the adhesion of the subsequent overlying tungsten layer. A barrier layer is preferably about 100 and 500 angstrom thick and more preferably about 300 angstrom thick.
Recent technology has found increased emphasis on mobile communication applications that center around compact high-frequency equipment. With the continued improvements in the performance characteristics of this equipment, continued emphasis will be placed on small size of the equipment, low power consumption, increased frequency applications and low noise levels. Semiconductor devices are used in the field of mobile communication for the creation of Radio Frequency (RF) amplifiers. A major component of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. The key challenge in the creation of the inductive and capacitive components is to minimize the surface area that is required for these components while maintaining a high Q value for the inductor and high storage capability for the capacitive component. Conventional inductors that are created on the surface of a substrate are of a spiral shape, whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations such as poor integration of the process that is used to create the inductor into a typical process of Integrated Circuit manufacturing. The common objectives that must be pursued in the creation of an inductor are to increase the quality value of the inductor, to increase the frequency of the LC self-resonance of the circuit thereby increasing the frequency range over which the inductor can be used, and to reduce the surface area that is required for the creation of the inductor.
The process of the invention addresses the above indicated objectives and problems by solving the typically experienced problems of planarity and etch stop on TaN, by solving topography problems that are typically experienced in creating stacked capacitors, and by solving problems of planarity and lack of uniformity of created trench thickness.
A typical processing sequence that is used for the formation of a metal-insulator-metal thin film capacitor is shown in FIG. 1. The MIM capacitor can be part of a multi-wiring structure whereby a multiplicity of elemental circuit elements such as diodes, field effect transistor, capacitors, resistors and inductors a located on the surface of a substrate forming footprints on this surface. Selective interconnection of these circuit elements by means of an patterned overlying layer of metal yields a device structure of a personalized nature that is dedicated to specific signal processing applications.
The Prior Art process of forming a MIM capacitor starts by depositing a first layer of insulation, layer 12, over the surface of a silicon substrate 10. The purpose of the layer of insulation is to insulate overlying devices and components from the underlying surface of the silicon substrate while at the same time providing for a means of connecting overlying devices of components to points of electrical contact in the surface of the substrate by selectively creating openings in the layer of insulation. A layer 14 of metal, typically aluminum, is deposited over the layer 12 of insulation, this layer of metal forms the lower plate of the to be created capacitor or can perform the function of an interconnect line (first level of interconnect wiring). For reasons of creating a smooth upper level surface of the lower capacitor plate, a conductive layer 16, typically of titanium nitride, is deposited over the surface of the layer 14 of metal. Layers 14 and 16 are patterned and etched using conventional methods of photolithographic exposure followed by an etch, creating in this manner the two platforms that are shown in FIG. 1b wherein one of the platforms, for instance layers 14a/16, is used for interconnect wiring or to form the first layer of a vertical inductor that can be created on the surface of substrate 10 while the second platform, for instance platform 14b/16, is further used for the creation of the MIM capacitor.
FIG. 1c shows the deposition and patterning of a second layer 18 of insulation whereby the patterning of layer 18 has removed that portion of the second insulation layer 18 and the insulation layer 16 that overlies the surface of the lower capacitor plate 14b.
A dielectric layer must next be provided for the MIM capacitor, a layer 20 of silicon oxide or any other dielectric is therefore blanket deposited over the structure of FIG. 1c, this layer must remain in place above the lower capacitor plate but must be removed above the contact point 14a in order to be able to establish contact with this point. Opening 17, FIG. 1e, is therefore created by patterning and selectively etching layers 20 and 18, contact opening 17 is aligned with and centered with respect to the underlying interconnect point 14a.
A conductive layer, typically aluminum, is next blanket deposited over the structure of FIG. 1e and patterned and etched thereby creating the contact plug 22a to the underlying point of electrical contact 14a further forming the upper capacitor plate 22b, see FIG. 1f.
The Prior Art method that has been detailed above for the formation of a MIM capacitor with the simultaneous formation of an electrical contact point has highlighted aluminum as a typical metal that can be used for the formation of the capacitor plates. Future technologies are however, for reasons that have been highlighted above, aimed at using copper as a material for the formation of the capacitor plates. The process of the invention addresses the formation of MIM capacitors whereby copper is used as the metal of choice for the capacitor plates and the thereby simultaneously created interconnect points (interconnect points that can also be used to further form layers of an inductor that is created vertically on the surface of a substrate). The Prior Art process that has been highlighted above under FIGS. 1a through 1f also has applied only one layer (layer 20, FIG. 1d and following) of dielectric in creating the dielectric for the MIM capacitor while the upper capacitor plate has for the example shown been aligned with the lower plate. These restrictions need not apply for other, more sophisticated capacitor designs as is shown in FIG. 2. FIG. 2 makes use of the basic premise that a capacitor contains two conducting media that are separated by a dielectric. The MIM capacitor that is shown contains the following elements:
10 the substrate on the surface of which the MIM capacitor is created PA1 24 a first layer of dielectric PA1 26 a second layer of dielectric PA1 28 a (copper) point of electrical contact that is provided in the surface of substrate 10 PA1 30 a (copper) plug that is aligned with copper plug 30 and that can serve as a partial construct of a (vertical) inductor that is created on the surface of the substrate 10 PA1 32 a (copper) point of contact that is provide in the surface of substrate 10 over which a MIM capacitor is to be created PA1 34 and 36 are two (copper) plugs that are provided in dielectric layer 24 and that align with point of contact 32 in the surface of substrate 10 PA1 38 and 40 are two (copper) plugs that are provided in dielectric layer 26 and that alien with copper plugs 34 and 36 respectively PA1 the layer 42/44/46 forms the dielectric of the MIM capacitor whereby the lower plate of the capacitor is formed by the copper plug combination 32/34/38 while the upper plate of the capacitor is formed by the copper plug combination 36/40. The stacked layer 42/44/46 is selected as such for reasons of creating the optimum dielectric (constant) ma-erial for the MIM capacitor, the materials used for this stacked dielectric are follows: layer 42 contains TaN, layer 44 contains SiO.sub.x or S.sub.x N.sub.y while layer 46 contains TaN. In creating the opening for plug 36, it is clear that layer 46 of TaN is used as the etch stop. A layer 46 of TaN, especially where the thickness of the layer is kept as thin as possible (to gain maximum capacitive value of the MIM capacitor), provides an unreliable etch stop potentially resulting in overetch and damage to the dielectric of the capacitor. In addition, the relative complexity of the three layers 42/44/46 makes it difficult to maintain good planarity on the surface of the stack of layers. Good planarity is required for reasons of reliability (too thin or a punctured dielectric makes the MIM capacitor prone to shorting between the two plates of the capacitor) and design (the dielectric of a capacitor must be uniformly distributed between the plates of the capacitor in order to provide dependable capacitive values). The process of the invention addresses these problems and provides a method whereby these problems are avoided.
U.S. Pat. No. 5,162,258 (Lemnios et al.) shows a process for a MIM capacitor. However, this reference differs from the invention.
U.S. Pat. No. 5,918,135 (Lee et al.) forms a MIM capacitor that does not use a standard barrier layer, see FIG. 7 and col. 4. Lee forms a capacitor dielectric layer over/through only 1 IMD layer.
U.S. Pat. No. 5,812,364 (Oku et al.), U.S. Pat. No. 5,920,775 (Koh) and U.S. Pat. No. 5,913,126 (Oh et al.) show other MIM processes.